Many CMOS integrated circuits utilize n.sup.+ gate material for both PMOS and NMOS devices. However, as gate lengths shrink, there is an increasing trend to the use of p.sup.+ gates for both PMOS and NMOS devices. PMOS transistors with p.sup.+ gates (i.e., surface channel devices) exhibit good short channel performance, threshold voltages, and sub-threshold swings which are less dependent upon channel length than PMOS devices with n.sup.+ (i.e., buried channel devices) gates. NMOS transistors with p.sup.+ gates have also been found satisfactory in various CMOS applications.
Some CMOS integrated circuits may utilize both n.sup.+ and p.sup.+ gates.
However, when a gate having an n.sup.+ doped region is in contact with a gate having a p.sup.+ doped region, interdiffusion of the dopants may occur, and there is an associated loss of control of the work function. The problem is expected to occur, for example, at those locations where a gate crosses a tub boundary. That portion of the gate over the p tub may be doped n+, while that potion of what is materially the same gate may be doped p.sup.+ over the n tub.
Some manufacturers have attempted to solve the problem by capping a continuous gate runner with a titanium nitride conductor, thus preserving conduction across the tub boundary should interdiffusion occur. However, with this approach, there is still a need to limit the thermal processing budget to retard the possibility of interdiffusion.